1. Field of the Invention
The present invention relates to a fabrication method of a thin film transistor, and more particularly, to a fabrication method of a thin film transistor using polycrystalline silicon.
2. Description of the Related Art
Generally, a thin film transistor (hereinafter referred to as “TFT”) includes a semiconductor active layer as one element thereof, which is of amorphous silicon or polycrystalline silicon.
The amorphous silicon may be deposited at a low temperature to form a thin film and is usually used in a switching device of a liquid crystal panel with a glass substrate having a low melting point.
When an amorphous silicon semiconductor layer containing hydrogen is used as a switching device and the semiconductor layer is exposed to light, a photocurrent is generated due to photoelectric conversion. Accordingly, current is generated in an off state. This fatally affects the operation of the switching device.
Even if the semiconductor layer is not exposed to light, many defects, such as dangling bonds that are a typical non-periodic lattice characteristic of amorphous silicon are generated and electrons do not flow naturally. As a result the performance of the device degrades. Accordingly, when forming a semiconductor layer using amorphous silicon, the electrical characteristics and reliability of the liquid crystal panel driving device deteriorate, and it is difficult to make the area of the display device large.
On the other hand, when polycrystalline silicon is used to form a semiconductor layer, the surface of the semiconductor layer has fewer defects. The operation speed of the TFT formed of polycrystalline silicon is about 100-200 times faster than that of the TFT formed of amorphous silicon.
Referring to FIGS. 1A through 1F, the process to fabricate a polycrystalline silicon TFT will be described. FIGS. 1A through 1F illustrate a method of fabricating a polycrystalline silicon TFT according to related art.
First, as shown in FIG. 1A, a buffer layer 102 is formed on a substrate 101. Here, the buffer layer 102 may be formed of one of insulating materials such as silicon oxide (SiO2), silicon nitride (SiNx), aluminum oxide (Al2O3) and the like. The buffer layer 102 provides a buffer between the substrate and the semiconductor layer to be formed later and prevents the substrate and the semiconductor layer from twisting because of nonuniform contact between the substrate and the semiconductor layer.
After that, an amorphous silicon layer 103 containing hydrogen is deposited on the buffer layer 102. The amorphous silicon layer 103 deposited on the buffer layer 102 is crystallized to form a semiconductor layer formed of polycrystalline silicon.
In general, to form the polycrystalline silicon layer, pure amorphous silicon is deposited with a thickness of about 500 Å and crystallized. A plasma chemical vapor deposition (CVD) or a low pressure CVD (LPCVD) may be used as a method to deposit an amorphous silicon layer.
There are a number of polycrystalline silicon forming methods using amorphous silicon, some of which are described below.
First, an amorphous silicon layer may be annealed at high temperature for a long time in a solid phase crystallization (SPC) method to form the polycrystalline silicon layer.
Second, metal may be deposited on the amorphous silicon in a metal induced crystallization (MIC) method to form the polycrystalline silicon layer, so that a large glass substrate may be used.
Third, polycrystalline silicon may be grown using a laser in laser annealing on the substrate on which an amorphous silicon layer is deposited.
The method of fabricating the TFT by using polycrystalline silicon layer will be described successively as follows. Referring to FIG. 1B, the crystallized polycrystalline layer is patterned to form a semiconductor layer 103a and inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx) may be deposited on an entire surface including the semiconductor layer 103a to form a first insulating film 104.
Then, as shown in FIG. 1C, a conductive material such as aluminum (Al) or Al alloy is deposited over the first insulating film 104 and patterned using photolithography to form a gate electrode 105 on a predetermined portion on the semiconductor layer 103a. 
Ions are implanted into the semiconductor layer 103a by using the gate electrode 105 as a mask to form a source/drain region. The semiconductor layer 103a is masked by the gate electrode 105, and the area of the semiconductor layer 103a into which ions are not implanted into becomes channel region.
As shown in FIG. 1D, after implanting ions, an inorganic insulating film is deposited on an entire surface including the gate electrode 105 to form a second insulating film 106. The second insulating film 106 and the first insulating film 104 are selectively removed to form a contact hole through which a predetermined portion of the source/drain region is exposed.
Then, as shown in FIG. 1E, conductive material such as Al or Al alloy is deposited on the second insulating film 106 through the contact hole and patterned in photolithography to form a source electrode 107 and a drain electrode 108 connected to the source/drain regions through the contact hole.
Finally, as shown in FIG. 1F, a passivation film 109 is deposited on the source electrode 107 and the drain electrode 108. A contact hole is formed in a region of the drain electrode 108 on the passivation film 109 and a pixel electrode 110 is formed to connect the pixel electrode 110 to the drain electrode 108.
Meanwhile, the electrical characteristic of the polycrystalline silicon TFT is affected greatly by grain morphology. In other words, the electric field effect mobility of the polycrystalline silicon TFT is increased as the size of the grains is increased.
FIG. 2 illustrates the size of grains according to the thickness of the general crystallized polycrystalline silicon layer. FIG. 3 illustrates characteristics of the TFT according to the thickness of the general polycrystalline silicon layer.
As shown in FIG. 2, it is well known that the amorphous silicon that is thinly formed at a thickness of 300-500 Å and crystallized has a small grain size, while the amorphous silicon that is thickly formed at a thickness of 1000-2000 Å and crystallized has a large grain size. As shown in FIG. 3, the mobility of the TFT is increased as the thickness of the polycrystalline silicon layer is increased. It is thought that the increase of the mobility is because the factors which hinder electrons from moving due to the increase of the size of the grains and the reduction of the defects in the grains are decreased.
In the method where the amorphous silicon is thickly formed at the thickness of 1000-2000 Å and the size of the crystallized grains is increased to improve the device characteristics, other problems arise.
For instance, as shown in FIG. 3, off current Ioff increases as the polycrystalline silicon layer gets thicker. When the polycrystalline silicon layer is thick, the generation-recombination region increases and leakage current increases.
In addition, when the polycrystalline silicon layer is thick, the gate metal line can be easily disconnected due to a high aspect ratio of the semiconductor layer (in the case of coplanar structure).